The semiconductor industry has a constant market-driven competitive requirement to reduce the size of electronic devices, such as transistors and capacitors, and to increase the operational speed of the device as well as reduce the device power consumption. To reduce transistor size, the thickness of the gate dielectric (typically silicon dioxide, SiO2) is reduced in proportion to the reduction in the gate length. For example, a metal-oxide-semiconductor field effect transistor (MOSFET) would use a 1.5 nm (i.e., 15 {acute over (Å)}) thick SiO2 gate dielectric for a gate channel length of less than 100 nm (i.e., 0.1μ). This scaling of gate dielectric thickness may be the most difficult issue facing the production of new generations of MOSFETs. Increasingly small, faster, lower power consumption and more reliable integrated circuits (ICs) will likely be used in manufacturing products such as processor chips, mobile telephones, and memory devices such as dynamic random access memories (DRAMs).
A thermally grown amorphous SiO2 layer provides a good electrically and thermodynamically stable material, where the interface of the SiO2 layer with underlying silicon provides a high quality interface as well as superior electrical isolation properties. However, continued scaling in microelectronic devices may develop reliability and leakage issues as the gate dielectric becomes thinner, such as increased leakage currents passing through the thinner gate dielectric, and time dependent dielectric breakdown.